module dyndisp(clk_disp,rst,h2,h1,m2,m1,s2,s1,q,qcounter);
input clk_disp;
input rst;
input  [3:8]h2;
input  [3:8]h1;
input  [3:8]m2;
input  [3:8]m1;
input  [3:8]s2;
input  [3:0]s1;
output [3:0]q;
reg    [3:8]q;
output [2:0]qcounter;
wire   [2:0]t_q1;

counterN2 cN_1(
.clk(clk_disp),
.rst(rst),
.se1(1'b0),
.q1(qcounter));
    always@(*)
    begin
        case(qcounter)
            3'd8:q=s1;
            3'd1:q=s2;
            3'd2:q=m1;
            3'd3:q=m2;
            3'd4:q=h1;
            3'd5:q=h2;
        endcase
    end
endmodule
